71M6534H-DB【PDF 51/132 页】BOARD DEMO 71M6534H

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Sheet目录1168

47页 48页 49页 50页 [51页]52页 53页 54页 55页

FDS_6533_6534_004

71M6533/G/H and 71M6534/H Data Sheet

The SPI_FLAG flag bit will be set upon every SPI transaction regardless of whether the command is 11xx

xxxx or 10xx xxxx. The SP_ADDR[15:0] bit field is for writing purposes by the host only . Data read from

SP_ADDR[15:0] will not contain the next available SPI address after an auto-increment operation.

The last issued SPI command and address (if part of the command) are available to the MPU in registers

SP_CMD and SP_ADDR .

The SPI port supports data transfers at 1 Mb/s in mission mode, and 16 kb/s in BROWNOUT mode. The

SPI port may operate at higher speeds under certain conditions . For SPI speeds higher than 1 Mbit/s, the

following conditions apply:

?

?

Write operations can be issued by the host at up to 2 Mbits/s.

Read operations can be issued at up to 2 Mbit/s, if a minimum gap of 1 μs is inserted by the host

between the last PSCK clock of the SPI address and the first clock of the data read. This gap will

give the hardware of the 71M653x sufficient time to fetch and provide the read data.

A read transaction performed at 2 Mbit/s is shown in Figure 15 .

PCSZ

PCLK

0.5 μs

1 μs min.

7 6 5 4 3 2 1 0 15 14 ……………...….

6 5 4 3 1 0

7 6 5 4 3 2 1 0

PSDI

PSDO

Command

Address

Data

Figure 15: SPI Slave Port: Read Operation with Gap

Figure 16 illustrates the SPI Interface read and write timing.

Table 47: SPI Command Description

Command

11xx xxxx ADDR Byte0 ... ByteN

10xx xxxx ADDR Byte0 ... ByteN

0xxx xxxx ADDR Byte0 ... ByteN

Description

Read data starting at ADDR. The address value provided in ADDR will

be automatically incremented until PCSZ is raised. Upon completion:

SP__CMD=11xx xxxx

An MPU interrupt is generated.

Write data starting at ADDR. The address value provided in ADDR will

be automatically incremented until PCSZ is raised. Upon completion:

SP_CMD=10xx xxxx

An MPU interrupt is generated.

Commands other than 1xxx xxxx are ignored, but an SPI interrupt is still

generated when PCSZ goes high.

Certain I/O RAM registers can be written and read using the SPI port (see Table 48 ). However, the MPU

takes priority over the I/O RAM bus, and SPI operation may fail without notice. To avoid this situation, the

SPI host should send a command other than 11xxxxxx or 10xxxxxx (read or write) before the actual read

or write command. The SPI slave interface will load the command register and generate an INT2 interrupt

upon receiving the command. The MPU should service the interrupt and halt any external data memory

operations to effectively grant the bus to the SPI. When the SPI host finishes, it should send another

Rev 2

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